Self-checking pulse transmission technique



Feb. 11, 1964 TIME I TIME I TIME 2 TIME TIME TIME 2 TIME I TIME I TIMTIME 2 IME I J. KELAR ETAL SELF-CHECKING PULSE TRANSMISSION TECHNIQUEFiled Aug. 3, 1960 -3so 02 ONE CAOCkI/VG Pee/0p (awe 60 Crcus Pave/op OE/6 MS) 2 Sheets-Sheet 1 TIME PER/OD 11v czoc/c Pan/o0 94 6406K PER/0D8/! Ct OCK 0 Pew/0a 7A neck 1/ Pea/0D 6 4 TIMES ac No II FEE/0D 54 TIMESclack PERIOD 4/; 0

C60 CK P452100 34 I II C(OCK 0 TIMES A li/I557" ORDEE 8/7 IN V EN TORSPIC/I420 A. DEA/4050M J'ose l/ Kane Nan/ 14 E2 .Dargaarr Feb. 1 1, 1964J. KELAR ETAL SELF-CHECKING PULSE TRANSMISSION TECHNIQUE Filed Aug. 3,1960 2 Sheets-Sheet 2 lrromvsv United States Patent 3 121,215SELF-CHEQIQNG PULE-E TRANSMESSEQN TEQHNEQUE Richard L. Dennison, andNorman E.

ma-"o gnome This invention relates to electric telemetering andcomputation and more particularly to a method or transmitting digitalpulse information from one location to another with self-cheering forreliability or" the transmitted information.

In transmitting coded information by electronic pulse means, there arethree types of errors which can reduce or destroy the reliability of thecode transmission. The first of these is human error in compiling orfeeding information to the equipment. The second source of error lies inmalfunction of the equipment itself, and the third is the false relayingof correct intelligence through equipment which is functioning properly.The tl ird situation is the most troublesome and is the most difficultto check since the influencing factors are not continuing or capable ofbeing stored so that they can be reviewed and scrutinized. The problemarises with the introduction of random pulses where there should benone, or the cancellation of pulses where they should be supplied. Theserandom effects are generically called noise and include an extraneousinfluence which will produce or obliterate pulses, such as inducedelectrical effects from other equipment, static or other naturalphenomena, all of which can produce discontinuous and unpatternedvoltage or current transients.

Out of a certain number of transmitted encoded characters, therepetition of the same received intelligence can be assumed as verifyingthe correctness of the intelligence. However, the greater the number or"inconsistent results as compared to consistent results, the lower is theprobability that the consistent results yield the true answer ormessage. Furthermore, such cut and try methods are purely empirical andare costly as Well as time consuming.

It is within the contemplation of the present invention and a generalobjecti e thereof to reduce to virtual certainty the recognition ofcorrect pulse code intelligence or the instantaneous reiection of falseintelligence upon reeption thereof.

More specifically, it is an obiect of the invention to provide a methodof true pu se code transmission which can be checked in the presence ofnoise while operating at a low level of pulse power.

A further c'oiect of the invention is to provide a technique forchecking the accuracy of pulse codes in the binary system wherein a timediiierential is selected to establish the unique difierence between abinary l and These and other objects and advantages of our inventionwill more fully appear from the following description, made inconnection with the accompanying d vings, wherein like referencecharacters refer to the s.rne or similar parts mroughout the severalviews and in which:

FIGURE 1 represents schematically a single clocking period for thecontrol logic and includes the clocking and pulsing times in relation toa sinusoidal wave;

FIGURE 2 is a diagrammatic representation of a transmission sequence forbinary coded decimal 25 using the pulse transmission technique of theinvention; and

FIGURE 3 is a block diagram of the transmitting and receiving stationsshowing the synchronized clock pulse Feb.

generation and the system by which the accuracy of transmission becomesself-checked.

Referring now to FIGURE 1, a single clocking period is represented as Aand includes a single cycle period typically associated with commercialelectrical current generation of 6% cycle power. The clocking mediumthus utilizes sinusoidal wave generation shown at it) and represents afull 369 for the clocking period which in the example shown constitutesor" a second. The beginning of the clocking period is shown at firsttime increment 11. All logical functions or data transfers within apiece of logic are accomplished during the clocking period A but notransmissions are made at the starting time 11. The first transmissionperiod occurs during the second time increment 12. During the timeincrement 12, a binary 1 may be transmitted onto the line. The timeincrement 12 occurs approximately 0 after starting time 11 and issynchronized substantially with the positive peak of sinusoidal waveit).

The sinusoidal wave then passes from positive to negative and the thirdtime increment 13 occurs at approximately 189" after the second timeincrement 12, or 276 after starting time 11. The time increment 13 isallocated to the transmission of a binary G and occurs at approximatelythe negative peak of sine wave 14 in the clocking period. The sine wavethen passes back from negative to positive and another clocking periodis begun with the first timing increment 11 followed by a secondclocking period and so forth. It is understood that the time incrementsallotted to binary ls and US may be interchanged.

In accordance with the present invention, provision is made to preventthe legal transmission of a binary 0 at time increment 12 or a binary lat time increment i3 and furthermore, provision is made arbitrarily toprevent legal transmission of both a binary 1 pulse and a binary 0 pulsein the same clocking period A. It will be observed that each clockingperiod A includes a couplet of pulsing positions and that the code pulsemust have its position distinguished within each clocking period. It istherefore possible to have one or more couplets in the same clockingperiod, if desired, in which case the time increment 12 would besubdivided into a plurality of such increments and similarly the timeincrement 13 would be subdivided into a similar number of distinct gatedtime increments. in any event, the transmission technique comprehendsonly couplets of positions and hence a specific time increment at 13must be paired with a specific time increment 12 in order to practicethe invention.

Referring now to FEGURE 2, a transmission sequence is shown by way ofexample for transmitting the binary coded decimal 25 which in binarycharacters is GGlGOlGl. it will be observed that throughout the sequenceof consecutive clocking periods 1A through 8A only one bit ofinformation is transmitted during one cloclc'ng period. Either binary lor binary 0 may be transmitted during a single clockin period but notboth. Should a pulse appear during both of time increments i2 and i3,signifying a binary l or 0 in the same clocking period, then thetransmission sequence is considered a fault and the entire message willbe rejected.

Gate generation circuits are utilized such that gate pulses withmanually controllable gate width are generated during second timeincrement 12 and third time increment 13. In order to produce a legalsignal, a pulse must be applied to the line during one of the gate timesoccurring t time increment 13. It is understood that signals will not bepassed at any other time during a clocking period. If the character of atransmitted signal is a simple pulse, a wide band network may beutilized at the receiver. If the transmitted signal is a pulse modulatedcarrier, a high Q tuned network may be employed at the receiver. While 3simple pulses and pulse modulated carriers may be employed, the latteris preferred because of the higher signal to noise ratio which improvesthe probability of producing an acceptable reception of the transmittedsignal in the presence of noise interference.

in carrying out the pulse transmission technique of the invention,reference is made to FIGURE 3. The transmission line circuit isindicated as lidand 15 and all functions are synchronized through clockpulse generation. In the diagram, the carrier generator and transmitter16 supplies synchronized pulses from the is pulse generator 17 and theOs pulse generator 18 as indicated.

Each of the pulse generators is provided with a phase shifter 19followed by a differentiating amplifier all and shaper amplifier 21 Eachof the pulse generators 17 and 18 is connected to the line 14, 15 andboth produce continuous trains of pulses, the pulses from generator 17being supplied for second time increment l2 and the generator 18supplying a like continuous train of pulses for third time increment 13in clocking period A of FIGURE 1. The clock pulse generator 22 providessynchronization with periodicity of frequencies at line 14-, 15. Clockpulse generator 22 employs in sequence, a wave form clipper 23 whichsquares sinusoidal wave forms from line 14, 15 so that they can bedifierentiated, a differentiating amplifier 24 which differentiates theoutput from clipper 23 in respect to time and simultaneously amplifiesthe pulses, and a shaper amplifier 25 which functions to further shapeand amplify the output of diiferentiating amplifier 24 to condition itfor practical use as shown in FIGURE 3. The synchronized pulses are thenfed to code register 26 where they affect DC. levels which representbinary TS and Os which have been previously inserted into the register26. These changing D.C. levels are applied to and gate 27 for the Ospulse generator 18, and to the and gate 28 for the 1s pulse generator17. The and gate 27 supplies pulses for channel 29 only when a pulse isreceived from generator 13 simultaneously with the proper D.C. levelfrom code register 26. Similarly, pulses are supplied to the 1 channelonly when a pulse is received from generator 1? simultaneously with theproper D.C. level from code register 26.

The Os pulse channel 29 and the 1s pulse channel 35) leads to the oramplifier 31 which controls the transmission of only one pulse for eachclocking period.

The block diagram elements in FIGURE 3 which have been described to thispoint constitute the transmitting portion of the system. The receivingportion also utilizes a clock pulse generator indicated at 32 whichsynchronizes the pulses from line 14, and renders the entire systemsynchronous with respect to the sinusoidal wave generation applied tothe line. As in the case of the transmitting portion of the system, thereceiving elements also include generators for PS and Os, the ls gategenerator being indicated at 33 and the Os gate generator beingindicated at 34. Generator 33 contains a phase shifter 35, adifferentiating amplifier 36 and a shaper amplifier 37 as shown.Similarly, the Os gate generator 34 is also provided with a phaseshifter 38, a difierentiating amplifier 39 and a shaper amplifier 4d.The and gate 41 extracts l pulses from generator 33 while the and gate42 extracts 0 pulses from generator 34. The gate generators 33 and 34-operate continuously to generate their respective gates at second timeincrement 12 and third time increment 13 of each clocking period asviewed in FIGURE 1, it being remembered that the entire system issynchronized through clock pulse generator 32 at the transmittinglocation and clock pulse generator 32 at the receiving portion.

A tuned RF amplifier and detector 43 is connected to line 14, 15 whichin turn extracts transmitted 1s and Os from the line and applies them toboth the and gate 41 and and gate 42. 1 pulses pass the and gate 41 onlywhen a simultaneous 1 pulse is received from the detector 43. Similarly,Os pass the and gate LII 42 only when a simultaneous pulse is receivedfrom detector 43. l and O pulses are supplied when passed from theirrespective gates to the input register 44 in which the codedintelligence is accumulated and stored for subsequent use. A faultdetector 45 receives all pulses from and gates 41 and 42 and analyzesthe received intelligence for fault conditions.

It thus may be seen that the clocking periods and transmission timescoupled with e arbitrary transmission laws and the synchronizing waveform produce a code transmission technique in which random noise willnot cause the equipment to accept erroneous information.

Referring again to FIGURE 2, at the start of clock period 1A, thereceiving equipment is preconditional for reception of information,therefore, it will be anticipating information between the start ofclock period 1A and the end of clock period 8A. Because of the arbitrarylaw utilized in the herein disclosed transmission technique, eachclocking period must contain only a 1 or a 0 and only at its properpoint in time, namely time increment 12 or time increment 13 in eachclocking period A. Should a clocking period occur that does not containa 1 pulse or a 0 pulse after the beginning of a transmission, the wholetransmission is considered erroneous and is rejected. Such fault istermed a no pulse fault signifying that something has happened and thetransmission has deviated from proper operation.

Under the second arbitrary rule or law set up in the transmissiontechnique of this invention, a 1 pulse and a 0 pulse can not both appearin the same clocking period A. If such a condition is indicated, thewhole transmission is considered erroneous and is rejected. Suchcondition is classed as a double pulse fault.

Detection of the no pulse fault and the double pulse fault can both beaccomplished through a single flip fiop circuit which, if not switchedduring a clocking period or if switched twice during a clocking period,can be made to signal the fault condition.

Referring again to FIGURE 2, in the clock period 1A, a 0 pulse wastransmitted at the third time increment while no pulse was transmittedat the second time increment. Supposing, however, that extraneous noiseshould create a pulse exactly at the gated second time increment 13 ofcloclr period 1A, no fault would be registered since a pulse was to havebeen transmitted at that time anywa It is to be observed that if anyextraneous noise occurs at any other time than during gated timeincrements 12 and 13, a pulse will not be received or recognized becauseof the narrow gating procedure utilized in the transmission technique.

Should noise eradicate a legitimate pulse, a no pulse fault would thenbe generated and again the transmission sequence would be rejected asfaulty. The only way in which the herein disclosed transmissiontechnique can be made to transmit a faulty signal from correctly appliedcode would be for pulse producing noise to occur at a no pulse position,that is, in exactly the proper phase, with an amplitude relation inrespect to the signal so as to generate a false signal at 1 timeincrement and then, within the same clocking period, to produce a noiseof particular character which would eradicate a legitimate signal so asto produce no pulse where one should exist. The probability of suchsimultaneous neutralizing and ignaling pulses occurring within the gatedtimes of a single clocking period is so remote as to be negligible inits influence on the accuracy of the self-checking character of theinstant invention.

It will, of course, be understood that various changes may be made inthe steps and their arrangement without departing from the scope of ourinvention as set forth in the appended claims.

What is claimed is:

1. A system for self-checking electronic pulse intelligence whichcomprises means for generating a clocking signal of preselectedfrequency, means for dividing the 3,1 5 clocking signal into clockingperiods each having distinct couplet positions, means for transmittin asuperposed code pulse at one position only of each of the coupletpositions, means for receiving the code pulse and distinguishing itsposition Within each period, and means for rejecting the receivedintelligence as false whenever code pulses occur at both pulse positionsWithin a clocking period and Whenever no pulse is received within aclocking period.

2. A system for self-checking electronic pulse intelligence whichcomprises means for generating a clocking signal of preselectedfrequency and of sinusoidal character, means for dividing the clockingsignal into clocking periods each having distinct couplet positionsrespectively at adjacent positive and negative sinusoids, means fortransmitting a superposed code pulse at one position only of each of thecouplet positions, means for receiving the code pulse and distinguishingits position within each period, and means for rejecting the receivedintelligence as false Whenever code pulses occur at both pulse positionsWithin a clocking period and whenever no pulse is received Within aclocking period.

3. A system for self-checking electronic pulse intelligence whichcomprises means for generating a clocking signal of preselectedfrequency and of sinusoidal character, means for dividing the clockingsignal into clocking periods each having distinct couplet positionsrespectively at the peak of a positive sinusoid and the peak of anadjacent negative sinusoid, means for transmitting a superposed codepulse at one position only of each of the couplet peak positions, meansfor receiving the code pulse and distinguishing its position Within eachperiod, and means for rejecting the received intelligence as falsewhenever code pulses occur at both pulse positions within a clockingperiod and whenever no pulse is received within a clocking period.

4. A system for self-checking electronic pulse intelligence whichcomprises means for generating a clocking signal of preselectedfrequency and of sinusoidal character, means for dividing the clockingsignal into clocking periods, each having a starting time approximatelyat a neutral point on the sinusoidal Wave signal, a pulsing timeincrement approximately 90 from starting time and another pulsing timeincrement approximately 180 from the first pulsing time increment, meansfor transmitting a superposed code pulse at one position only of each ofthe couplet pulsing time increments, means for receiving the code pulseand distinguishing its position within each period, and means forrejecting the received intelligence as false whenever code pulses occurat both pulse positions within a clocking period and Whenever no pulseis received Within a clocking period.

5. The system as set forth in claim 2 wherein all of the pulsing atpositive sinusoid positions represent one class of binary 1s and binary0s and all of the pulsing at negative sinusoid positions represent theother class of binary 1s and binary 0s.

6. The system as set forth in claim 4 wherein all of the 90 incrementsrepresent one of a binary 1 and a binary 0 and all of the 180 incrementsrepresent the other of the binary 1 and a binary 0.

7. A system for self-checking electronic pulse intelligence comprisingmeans for transmitting a code pulse at either of two distinct timepositions within a predetermined time period, means for receiving thecode pulse and distinguishing its position Within said period, and meansfor rejecting the received intelligence as false whenever code pulsesoccur at both pulse positions Within said period and whenever no pulseis received within said period.

8. The systems as set forth in claim 7 wherein the code pulse for one ofsaid distinct time positions is a positive pulse and a negative pulsefor the other of said time positions.

References Cited in the tile of this patent UNITED STATES PATENTS2,706,215 Van Duuren Apr. 12, 1955 2,707,209 Ambrosio Apr. 26, 19552,844,721 Minkow July 22, 1958

1. A SYSTEM FOR SELF-CHECKING ELECTRONIC PULSE INTELLIGENCE WHICHCOMPRISES MEANS FOR GENERATING A CLOCKING SIGNAL OF PRESELECTEDFREQUENCY, MEANS FOR DIVIDING THE CLOCKING SIGNAL INTO CLOCKING PERIODSEACH HAVING DISTINCT COUPLET POSITIONS, MEANS FOR TRANSMITTING ASUPERPOSED CODE PULSE AT ONE POSITION ONLY OF EACH OF THE COUPLETPOSITIONS, MEANS FOR RECEIVING THE CODE PULSE AND DISTINGUISHING ITSPOSITION WITHING EACH PERIOD, AND MEANS FOR REJECTING THE RECEIVEDINTELLIGENCE AS FALSE WHENEVER CODE PULSES OCCUR AT BOTH PULSE POSITIONSWITHIN A CLOCKING PERIOD AND WHENEVER NO PULSE IS RECEIVED WITHIN ACLOCKING PERIOD.